This application is related to Japanese application No. 2001-185548 filed on 19 Jun. 2001, whose priority is claimed under 35 USC xc2xa7119, the disclosure of which is incorporated by reference in its entirety.
1. Field of the Invention
The present invention relates to a semiconductor device and its manufacturing method, and more particularly to a semiconductor device formed on an SOI (Silicon On Insulator) substrate and its manufacturing method.
2. Description of the Prior Arts
A basic CMOS (Complementary Metal Oxide Semiconductor)/SRAM (Static Random Access Memory) cell conventionally used has, as shown in FIG. 1, a flipflop circuit comprising two load PMOS transistors 100, 101 and two driving NMOS transistors 102, 103 as well as two transfer NMOS transistors 104, 105.
The CMOS/SRAM cell of this type has a structure shown in FIGS. 8(a) and 8(b). Specifically, a p-well region 113 and n-well region 114 are formed in a silicon substrate 112 via a device isolating oxide film 117. An NMOS transistor 115 is formed at an active region in the p-well region 113, while a PMOS transistor 116 is formed at an active region in the n-well region. Provided on each surface of the p-well region 113 and n-well region 114 are p+ diffusion layer 118 and n+ diffusion layer 119, respectively. The p-well region 113 is grounded via the p+ diffusion layer 118, while the n-well region 114 is supplied with Vdd potential via the n+ diffusion layer 119. This brings a pn-junction between the p-well region 113 and the n-well region 114 into a reverse-bias state, thereby realizing a device isolation.
The CMOS/SRAM of this type has a problem of the occurrence of soft error due to alpha-ray. This becomes a subject for realizing a highly reliable device.
Specifically, a LSI chip on which CMOS/SRAM is formed is generally sealed with a resin for use. A neutron produced due to alpha-ray or cosmic rays emitted from an radioactive element included in the resin that is a sealing material is sometimes incident to the LSI chip. As shown in FIG. 8(b), this alpha-ray or neutron causes an electron-hole pair 120 in the silicon substrate 112 by an electrolytic dissociation. These electrons and holes are respectively drawn by a positive potential and negative potential and move in the silicon substrate 112. For example, electrons are drawn to the drain region that is biased to a positive potential in the case of NMOS transistor. When the electrons or holes produced by alpha-ray invade into a data storing node of the SRAM cell, the node potential is inverted thereby causing a malfunction such as data rewriting.
An SOI/CMOS technique has been proposed with respect to this. The SOI/CMOS circuit, as shown in FIG. 9, does not require the formation of a well used for isolating the n+ diffusion layer formed p+ diffusion layer although the above-mentioned bulk CMOS/SRAM cell circuit requires the formation of the well. In the SOI/CMOS circuit, a MOS transistor or diffusion layer is formed on a silicon layer above an insulating film 121. Each element is perfectly isolated from the substrate by this insulating film 121. Accordingly, electron-hole pair 120 produced in the bulk substrate due to alpha-ray does not give an influence to each element, whereby data is hardly rewritten.
Japanese Unexamined Patent Application No. HEI7-153854 discloses an SOI/SRAM cell structured such that source/drain regions of a load PMOS transistor and driving NMOS transistor which are adjacent to each other directly forms a PN-junction. This application also discloses that a well isolation or contact (corresponding to 110d, 110g in FIG. 8(a)) is unnecessary because of this PN-junction, resulting in being capable of reducing the cell area.
A transistor fabricated on the SOI substrate is classified into two types in view of its structure, i.e., into a full depletion type and a partial depletion type. Specifically, the maximum value of the width of the depletion layer (maximum depletion layer width) is determined according to an impurity concentration implanted into a silicon layer at a channel region of the SOI. A transistor wherein the maximum depletion layer width is greater than the thickness of the silicon layer at the channel region is called a full depletion type SOI transistor, while a transistor wherein the maximum depletion layer width is smaller than the thickness of the silicon layer at the channel region is called a partial depletion type SOI transistor.
As for the transistor fabricated on the SOI substrate, a parasitic capacitance (junction capacitance) between a drain and a substrate can be reduced. In the case of a full depletion type SOI transistor wherein a thickness of a silicon layer is made thin such as the same as or smaller than approximately 50 nm, in particular, a short channel effect (a reduction in a threshold voltage with the decrease in a gate length and increase in subthreshold coefficient) can be reduced, whereby a substrate floating effect hardly occurs. Therefore, a merit of the full depletion type SOI transistor can be greatly enjoyed by a high-technology device of a microstructural level wherein a body contact is unnecessary and a layout area can be reduced, compared to a partial depletion type transistor wherein a body contact is generally required.
However, as a memory cell is reduced and voltage is lowered, an electric current which can be supplied to the memory cell is decreased. Therefore, it is difficult to ensure a soft error resistance. Even the SOI structure is insufficient for satisfying a demand for a super highly reliability of a general {fraction (1/1000)} level with respect to the incident of low-energy alpha-ray that produces electron-hole pairs at the shallow region of the substrate surface. This fits the full depletion type SOI structure having thinner body region.
The silicon layer of the SOI substrate becomes electrically a floating state in the SOI structure. Therefore, a parasitic bipolar transistor occurs in the MOS transistor fabricated on the silicon layer. For example, an npn-type parasitic bipolar transistor occurs in the NMOS transistor by a p-type channel region and n-type source/drain regions.
In case where electron-hole pairs 120 are produced at the channel region due to alpha-ray when data is stored, electrons are drawn out into the drain in the npn-type parasitic bipolar transistor as shown in FIG. 10. On the other hand, holes are accumulated on the channel region. This channel region corresponds to a base of the npn-type parasitic bipolar transistor. Accordingly, a potential of the base rises up due to the accumulated holes, thereby operating the npn-type parasitic bipolar transistor. As a result, the NMOS transistor is turned on, whereby the potential of data storing node decreases for reversing the stored data.
The present invention is accomplished in view of the above circumstances, and aims to provide a semiconductor device provided with a highly reliable CMOS/SRAM cell using an SOI substrate having an excellent soft error resistance, and its manufacturing method.
The present invention provides a semiconductor device comprising:
an SOI substrate having a surface semiconductor layer,
a gate electrode formed on the surface semiconductor layer via a gate insulating film,
first conductive type source/drain regions formed in the surface semiconductor layer of both sides of the gate electrode,
a second conductive type drawing diffusion layer formed in the surface semiconductor layer and contacted with at least one of the first conductive type source/drain regions, and
a silicide layer which is formed on the surface semiconductor layer to partially or entirely overlie both said at least one of source/drain regions and the drawing diffusion layer, the silicide layer being grounded.
Further, the present invention provides a semiconductor device comprising:
an SOI substrate having a surface semiconductor layer,
a gate electrode formed on the surface semiconductor layer via a gate insulating film,
first conductive type source/drain regions formed in the surface semiconductor layer of both sides of the gate electrode,
a second conductive type drawing diffusion layer formed in the surface semiconductor layer and contacted with at least one of the first conductive type source/drain regions, and
a first conductive type impurity diffusion layer which is formed in the surface semiconductor layer and adjacent to the drawing diffusion layer, the first and conductive type impurity diffusion layer being grounded.
Moreover, the present invention provides a method for manufacturing a semiconductor device having a CMOS transistor on a SOI substrate comprising:
(a) forming a gate electrode on the SOI substrate via a gate insulating film;
(b) forming a resist mask having an opening at a region where a second conductive type drawing diffusion layer is formed and a region where a second conductive type MOS transistor is formed, and ion-implanting a second conductive type impurity by using the mask to form a second conductive type source/drain regions and the second conductive type drawing diffusion layer, and
(c) forming a first conductive type source/drain region at the region where the first conductive type MOS transistor is formed, and ion-implanting a first conductive type impurity.
These and other objects of the present application will become more readily apparent from the detailed description given hereinafter. However, it should be understood that the detailed description and specific examples, while indicating preferred embodiments of the invention, are given by way of illustration only, since various changes and modifications within the spirit and scope of the invention will become apparent to those skilled in the art from this detailed description.